Resistor Modeling in Verilog-A #verilog #vlsi
1:13
YouTubeCadence Design Systems
Resistor Modeling in Verilog-A #verilog #vlsi
Want to understand how real circuit physics like Ohm’s law can be modeled directly in Verilog‑A? Learn behavioral modeling the right way Enroll in the course: https://www.cadence.com/en_US/home/training/all-courses/82086.html Mixed-Signal Design Modeling, Simulation and Verification Courses: https:;//www.cadence.com/en_US/home/training ...
650 views1 month ago
Shorts
Học Ngành Vi Mạch Bán Dẫn: Cơ Hội và Thách Thức
6:39
106.9K views
Học Ngành Vi Mạch Bán Dẫn: Cơ Hội và Thách Thức
thayquyethuongnghiep
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL)
0:23
635 views
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders
Sly Fox electronics
Verilog Basics
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
1:03
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
YouTubeCadence Design Systems
1.9K views3 months ago
Trigger Events on Time with @timer operator #eda #cadence #chipdesign
1:03
Trigger Events on Time with @timer operator #eda #cadence #chipdesign
YouTubeCadence Design Systems
276 views1 month ago
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
2:57
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
YouTubeChip Logic Studio
1.5K views4 months ago
Top videos
Master the 2:1 Multiplexer! 🔀⚡ | Verilog Code + Testbench + Waveform (Vivado FPGA Tutorial) Review
0:22
Master the 2:1 Multiplexer! 🔀⚡ | Verilog Code + Testbench + Waveform (Vivado FPGA Tutorial) Review
YouTubeSly Fox electronics
185 views1 month ago
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL) [short]
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL) [short]
YouTubeSly Fox electronics
84 views2 months ago
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
2:52
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
YouTubeChip Logic Studio
695 views5 months ago
Verilog Examples
Verilog Day 1: Introduction and Data Types Explained from Scratch
2:59
Verilog Day 1: Introduction and Data Types Explained from Scratch
YouTubeChip Logic Studio
103 views9 months ago
Verilog Day 1: Introduction and Data Types Explained from Scratch
2:21
Verilog Day 1: Introduction and Data Types Explained from Scratch
YouTubeChip Logic Studio
242 views9 months ago
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
2:57
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
YouTubeChip Logic Studio
171 views5 months ago
Master the 2:1 Multiplexer! 🔀⚡ | Verilog Code + Testbench + Waveform (Vivado FPGA Tutorial) Review
0:22
Master the 2:1 Multiplexer! 🔀⚡ | Verilog Code + Testbench + Waveform (Vivado FPGA Tutorial) Review
185 views1 month ago
YouTubeSly Fox electronics
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL) [short]
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL) [short]
84 views2 months ago
YouTubeSly Fox electronics
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
2:52
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
695 views5 months ago
YouTubeChip Logic Studio
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL)
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL)
635 views6 months ago
YouTubeSly Fox electronics
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
1:03
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
1.9K views3 months ago
YouTubeCadence Design Systems
Trigger Events on Time with @timer operator #eda #cadence #chipdesign
1:03
Trigger Events on Time with @timer operator #eda #cadence #chipdesign
276 views1 month ago
YouTubeCadence Design Systems
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
2:57
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
1.5K views4 months ago
YouTubeChip Logic Studio
2:55
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
116 views4 months ago
YouTubeChip Logic Studio
2:51
Verilog Timing Control | Delay Control and Event Synchronization
227 views6 months ago
YouTubeChip Logic Studio
1:24
Difference between Data types of Verilog and SystemVerilog #cadence #chipdesign
1.1K views3 months ago
YouTubeCadence Design Systems
1:07
Digital Versus Analog: Inverter Modeling, Unpacked #vlsi #coding #asicdesign
640 views2 months ago
YouTubeCadence Design Systems
6:39
Học Ngành Vi Mạch Bán Dẫn: Cơ Hội và Thách Thức
106.9K views11 months ago
TikTokthayquyethuongnghiep
0:54
LÀM CHIP KHÓ LẮM SAO? LỘ TRÌNH 6 BƯỚC ĐỂ TRỞ THÀNH KỸ SƯ THIẾT KẾ IC! ⸻ 1. Thiết kế IC là gì? \t•\tThiết kế IC (Integrated Circuit) là quá trình biến ý tưởng thành vi mạch điện tử. \t•\tGồm 2 mảng chính: \t•\tFront-end: Thiết kế logic – viết code mô tả phần cứng (Verilog/VHDL). \t•\tBack-end: Triển khai layout – thiết kế hình dạng vật lý con chip. ⸻ 2. Lộ trình học chi tiết – Từng bước thực tế: Bước 1: Nắm chắc kiến thức điện tử cơ bản \t•\tMạch điện – điện tử: Op-amp, logic gates, CMOS, MOSFET.
65.2K viewsApr 25, 2025
TikTokongbobitcoin
0:10
Engineer's Guide to Coding and Electronics for Women in STEM
61.9K viewsSep 14, 2023
TikTokaiszzyelectronics
0:15
FPGA para aplicaciones espaciales
18.2K viewsJun 29, 2025
TikTokcapsula.electronica
0:49
You NEED a complete and up to date LinkedIn profile in 2026. LinkedIn is essentially a search engine for recruiters—if your profile doesn’t have the right keywords, you won’t be found or considered for interviews. To fix this, you need to: 🔑 Target Keywords: Add technical skills like (ex. Python, Verilog, or UVM) to your headline, about section, and experience. 🖼️ Build a Portfolio: Don’t just list skills—post photos of your hardware builds or screen recordings of your code. 📄 Pin Your Resume
4K views7 months ago
TikTokengcalebj28
0:12
FPGA Project: 7 Segment LED Display with Verilog
5.5K views11 months ago
TikTokfurt_tech
0:10
Stratosky FPGA - Rumbo a México
3.3K views6 months ago
TikTokcapsula.electronica
0:35
FPGAs Peruanas: Prototipo Oficial y Entrenamiento
10.7K viewsNov 12, 2024
TikTokcapsula.electronica
See more
Static thumbnail place holder

Short videos

1:13
Resistor Modeling in Verilog-A #verilog #vlsi
650 views1 month ago
YouTubeCadence Design Systems
0:22
Master the 2:1 Multiplexer! 🔀⚡ | Verilog Code + Testbench + Waveform (Vivado FPGA
185 views1 month ago
YouTubeSly Fox electronics
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation +
84 views2 months ago
YouTubeSly Fox electronics
2:52
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginner
695 views5 months ago
YouTubeChip Logic Studio
6:39
Học Ngành Vi Mạch Bán Dẫn: Cơ Hội và Thách Thức
106.9K views11 months ago
TikTokthayquyethuongnghiep
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL
635 views6 months ago
YouTubeSly Fox electronics
1:03
Synthesizable vs Non Synthesizable Verilog #cadence #chipdesign
1.9K views3 months ago
YouTubeCadence Design Systems
1:03
Trigger Events on Time with @timer operator #eda #cadence #chipdesign
276 views1 month ago
YouTubeCadence Design Systems
2:57
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
1.5K views4 months ago
YouTubeChip Logic Studio
2:55
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
116 views4 months ago
YouTubeChip Logic Studio
2:51
Verilog Timing Control | Delay Control and Event Synchronization
227 views6 months ago
YouTubeChip Logic Studio
1:24
Difference between Data types of Verilog and SystemVerilog #cadence #chipdesign
1.1K views3 months ago
YouTubeCadence Design Systems
1:07
Digital Versus Analog: Inverter Modeling, Unpacked #vlsi #coding #asicdesign
640 views2 months ago
YouTubeCadence Design Systems
0:54
LÀM CHIP KHÓ LẮM SAO? LỘ TRÌNH 6 BƯỚC ĐỂ TRỞ THÀNH KỸ SƯ THIẾT KẾ IC!
65.2K viewsApr 25, 2025
TikTokongbobitcoin
0:10
Engineer's Guide to Coding and Electronics for Women in STEM
61.9K viewsSep 14, 2023
TikTokaiszzyelectronics
0:15
FPGA para aplicaciones espaciales
18.2K viewsJun 29, 2025
TikTokcapsula.electronica
0:49
You NEED a complete and up to date LinkedIn profile in 2026. LinkedIn is essentially a
4K views7 months ago
TikTokengcalebj28
0:12
FPGA Project: 7 Segment LED Display with Verilog
5.5K views11 months ago
TikTokfurt_tech
0:10
Stratosky FPGA - Rumbo a México
3.3K views6 months ago
TikTokcapsula.electronica
0:35
FPGAs Peruanas: Prototipo Oficial y Entrenamiento
10.7K viewsNov 12, 2024
TikTokcapsula.electronica
Static thumbnail place holder