News

Design-Reuse6h
Worldwide Silicon Wafer Shipments and Revenue Fall in 2023, SEMI Reports
MILPITAS, Calif. — February 7, 2024 — Worldwide silicon wafer shipments in 2023 decreased 14.3% to 12,602 million square inches while wafer revenue contracted 10.9% to $12.3 billion over the same ...
Design-Reuse7h
Electronic System Design Industry Posts $4.5 Billion in Revenue in Q1 2024, ESD Alliance Reports (PRNewsfoto/SEMI)
MILPITAS, Calif. -- July 16, 2024-- Electronic System Design (ESD) industry revenue increased 14.4% to $4,521.6 million in the first quarter of 2024 from the $3,951.1 million registered in the first ...
Design-Reuse8h
Video LVDS SerDes Transmitter / Receiver IP Core
The Video LVDS SerDes Transmitter / Receiver IP Core provides a complete, easy-to-use Serializer/Deserializer (SerDes) solution to interface a wide variety of video host systems to Flat Panel displays ...
Design-Reuse8h
Xylon Unveils 2D and 3D Graphics/HMI logicBRICKS Reference Designs for Xilinx Zynq-7000 ZC702 Evaluation Board
Zagreb, Croatia, August 2, 2012 – Xylon d.o.o., a leading provider of advanced FPGA application solutions and IP cores, demonstrates 2D and 3D Graphics Processing Units (GPU) for Xilinx® Zynq™-7000 ...
Design-Reuse8h
DFI Group Releases Initial Version of the DFI 5.0 Specification for High-Speed Memory Controller and PHY Interface
AUSTIN, Texas, May 2, 2018 — The DDR PHY Interface (DFI) Group today released version 5.0 of the specification for interfaces between high-speed memory controllers and physical (PHY) interfaces to ...
Design-Reuse8h
MIPI Alliance Completes Development of A-PHY v1.0, an Industry-Standard Long-Reach SerDes Physical Layer Interface for Automotive Applications
Specification designed to accelerate ADAS, ADS and IVI automotive connectivity enters final approval phase, with release expected in 90 days PISCATAWAY, N.J., June 3, 2020—The MIPI Alliance, an ...
Design And Reuse8h
Siemens to bring advanced timing constraint capabilities to EDA design flow with Excellicon acquisition
Acquisition enables System-on-a-Chip (SoC) designers to accelerate design closure and enhance functional and structural constraint correctness with industry-proven timing constraints management Plano, ...
Design And Reuse10h
RISC-V Technology Seeing Growing Maturity and Penetration
An interesting data point presented by analyst Richard Wawrzyniak of the SHD Group highlighted the growing maturity and penetration of RISC-V technology: an expected flip from license-driven revenue ...
Design And Reuse10h
Synopsys Interconnect IPs Enabling Scalable Compute Clusters
This strategic collaboration will leverage Synopsys' expertise in silicon IPs to assist in the development of bespoke AI silicon, forming the foundation for advanced compute clusters aimed at deliveri ...
Design And Reuse10h
Secure-IC at Computex 2025: Enabling Trust in AI, Chiplets, and Quantum-Ready Systems
In a landscape defined by AI acceleration , chiplet-based system integration, and upcoming post-quantum challenges, Secure-IC ...
Design And Reuse17h
InPsytech Joins Samsung SAFE™ IP Partner Program for Excellence in ONFI and UCIe IP Solutions
The Samsung SAFE™ program is designed to foster close collaboration between Samsung Foundry and its partners, encouraging innovation and efficiency across the semiconductor design ecosystem. By ...
Design And Reuse18h
Codasip: Toward Custom, Safe, Secure RISC-V Compute Cores
In a keynote speech at the RISC-V Summit Europe 2025 in Paris, Emmanuel Till-Vattier, VP of sales EMEA at Codasip, presented a brief product update, including new possibilities for fast migration from ...