EDN

Cadence promises full SystemVerilog support

SAN JOSE, Calif. — As 26 EDA vendors presented their plans for SystemVerilog support at the Design Automation Conference last week, Cadence Design Systems was notably missing. But Cadence, which ...
EDN

Cadence sets support for SystemVerilog

Santa Cruz, Calif. – Cadence Design Systems Inc. has presented an initial timetable for its support of SystemVerilog, proposed by the Accellera standards organization as the next generation of the ...
Design-Reuse

Cadence and Mentor Announce Immediate Availability of the Open Verification Methodology

SAN JOSE, CA and WILSONVILLE, OR -- Jan 9, 2008 -- Cadence Design Systems, Inc. and Mentor Graphics Corp. today announced immediate availability of the Open Verification Methodology (OVM), which was ...
Electronic Design

Cadence, Mentor Graphics agree on SystemVerilog verification

Cadence Design Systems (www.cadence.com) and Mentor Graphics (www.mentor.com) have agreed to standardize on an open source methodology for verifying SystemVerilog design files. Cadence Design Systems ...
Business Wire

Cadence and Mentor Graphics Deliver Interoperability with Open SystemVerilog Verification Methodology

SAN JOSE, Calif., & WILSONVILLE, Ore.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ:CDNS), and Mentor Graphics Corp. (NASDAQ:MENT) today announced that they will standardize on a verification ...
Design-Reuse

Cadence Delivers OVM-Compliant Verification IP

SAN JOSE, Calif. -- Jun 09, 2008 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced the availability of the first two advanced testbench ...
Electronic Design

Cadence And Mentor Develop Open-Source SystemVerilog Methodology

EDA giants Cadence Design Systems and Mentor Graphics announced that they will create and standardize on a verification methodology based on the IEEE 1800(TM)-2005 SystemVerilog standard. Using the ...