Managing the power consumption of ICs is an increasingly difficult challenge, because each new generation of portable device includes expanded features and demands longer battery lives.

Wire delay is beginning to dominate gate delay in current CMOS technologies. According to Moore’s Law by 2016 CMOS feature size should be on the order of 22 nm with clock frequencies reaching around ...

We knew that our innovative asynchronous chip architecture could improve system efficiency by increasing performance and decreasing power consumption. But we had to show prospective customers that it ...

Asynchronous, or clockless, logic–an alternative to standard digital circuits that avoids many of their problems–is beginning to look attractive for embedded designs in consumer electronics and mobile ...

As the quest grows to manage power in everything from the handheld smart phone to sensors for automotive applications and contactless payment cards, designers are getting hungry for new design ...

Inhibitory cortical neurons are thought to generate temporally precise signals important for information processing, but a new study shows that CCK-expressing interneurons continue to release GABA for ...

There are a number of interesting technologies to keep an eye on in term of how and when they could be adopted for use in SoC design today, some of which include gallium arsenide, GPGPUs, 3D ICs and ...