EDN

Detect wire breaks with unusual CMOS gate circuit

CMOS devices have large input impedance with input currents on the order of 0.01nA. Adding feedback circuitry can result in a latch-like device that can be used to store bits, and also operate in a ...
TechRepublic

Power Optimization of 8:1 MUX Using Transmission Gate Logic (TGL) with Power Gating Technique

In this paper, the authors aim at reducing power and energy dissipation in Transmission Gate Logic (TGL) multiplexer CMOS circuits comprise of reducing the power supply voltages, power supply current ...
Electronic Design

Layout-Dependent Modeling Boosts CMOS Gate Density

A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...
EDN

Rethink fault models for submicron-IC test

The electronics industry is in the midst of a transformation that is drastically changing product design and manufacture. Deep submicron process technology puts more gates on a chip, and the ...